Espressif Systems /ESP32-P4 /I3C_MST /DATA_BUFFER_THLD_CTRL

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Interpret as DATA_BUFFER_THLD_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0REG_TX_DATA_BUF_THLD 0REG_RX_DATA_BUF_THLD

Description

NA

Fields

REG_TX_DATA_BUF_THLD

Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31

REG_RX_DATA_BUF_THLD

Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31

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